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- 2019
-
Mark
Test Flow Selection for Stacked Integrated Circuits
SenGupta, Breeta LU ; Nikolov, Dimitar LU ; Dash, Assmitra and Larsson, Erik LU
(2019)
In Journal of Electronic Testing: Theory and Applications
35(4).
p.425-440
- Contribution to journal › Article
- 2014
-
Mark
Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning and Test Access Mechanism Design for 3D SICs
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Test Planning for 3D SICs using ILP
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2012)
2012 25th International Conference on VLSI Design
p.442-447
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2012)
IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding