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        - 2018
- 
                        Mark
        A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
    
    - Contribution to journal › Article
 
- 2017
- 
                        Mark
        A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS
    
    - Contribution to journal › Article
 
- 2016
- 
                        Mark
        A 1.5 V 28 GHz beam steering SiGe PLL for an 81-86 GHz E-band transmitter
    
    - Contribution to journal › Article
 
- 2009
- 
                        Mark
        A PLL based 12GHz LO generator with digital phase control in 90nm CMOS
    
    - Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
 
