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- 2011
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
(2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)
- Contribution to conference › Paper, not in proceeding
