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2017
Mark Digital Phase Locked Loops for Radio Frequency Synthesis
Mahmoud, Ahmed ^LU (2017)
- Thesis › Doctoral thesis (monograph)
2016
Mark A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise
Wu, Ying ; Shahmohammadi, Mina ; Chen, Yue ; Lu, Ping ^LU and Staszewski, Robert Bogdan (2016) 42nd European Solid-State Circuits Conference, ESSCIRC 2016 2016-October. p.209-212
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
Mahmoud, Ahmed ^LU ; Andreani, Pietro ^LU and Lu, Ping ^LU (2016) In Analog Integrated Circuits and Signal Processing 89(2). p.337-345
- Contribution to journal › Article
2015
Mark A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise
Mahmoud, Ahmed ^LU ; Andreani, Piero ^LU and Lu, Ping ^LU (2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2014
Mark A 1-1 MASH 2-D Vernier Time-to-Digital Converter with 2nd-order noise shaping
Lu, Ping ^LU and Andreani, Pietro ^LU (2014) IEEE International Symposium on Circuits and Systems (ISCAS), 2014 p.1324-1327
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2013
Mark A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
Lu, Ping ^LU ; Liscidini, Antonio and Andreani, Pietro ^LU (2013) Norchip conference, 2012
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2011
Mark A mixed mode design flow for multi GHz ADPLLs
Shakir, Muhammad ; Abdulaziz, Mohammed ^LU ; Lu, Ping ^LU and Andreani, Pietro ^LU (2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding

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