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- 2017
-
Mark
Digital Phase Locked Loops for Radio Frequency Synthesis
(2017)
- Thesis › Doctoral thesis (monograph)
- 2016
-
Mark
A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
- Contribution to journal › Article
-
Mark
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2015
-
Mark
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise
(2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
A 1-1 MASH 2-D Vernier Time-to-Digital Converter with 2nd-order noise shaping
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
(2013) Norchip conference, 2012
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2011
-
Mark
A mixed mode design flow for multi GHz ADPLLs
(2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding