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- 2011
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
A technique for improving gain and noise figure of common-gate wideband LNAs
(
- Contribution to journal › Article
-
Mark
A 90-nm CMOS +11dBm IIP3 4mW dual-band LNA for cellular handsets
(
- Contribution to journal › Letter
-
Mark
A 4.35-mW +22-dBm IIP3 continuously tunable channel select filter for WLAN/WiMax receivers in 90-nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
K-band receiver front-ends in 0.13um CMOS using carrier technology
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 175uW 100MHz-2GHz inductorless receiver frontend in 65nm CMOS
2010) NORCHIP Conference, 2010(
- Contribution to conference › Paper, not in proceeding
- 2009
-
Mark
Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters
(
- Contribution to journal › Article
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
60 GHz 130-nm CMOS Second Harmonic Power Amplifiers
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding