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- 2012
-
Mark
Re-using Chip Level DFT at Board Level
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2008
-
Mark
Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Optimization with Compression-Technique Selection
2008) A Workshop in Conjunction with the International Test Conference(
- Contribution to conference › Paper, not in proceeding
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977(
- Contribution to journal › Article
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2006
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding