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- 2017
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Mark
The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs
2017) 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 2017-September. p.273-276(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2015
-
Mark
Template-assisted selective epitaxy of III-V nanoscale devices for co-planar heterogeneous integration with Si
(
- Contribution to journal › Article
- 2014
-
Mark
III-V semiconductor nanowires for future devices
2014) 17th Design, Automation and Test in Europe, DATE 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding