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- 2010
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Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cells Reordering to Minimize Peak Power During Test Cycle : A Graph Theoretic Approach
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2009
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Capture Power Reduction for Modular System-on-Chip Test
2009) IEEE/VSI VLSI Design and Test Symposium (VDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
(
- Contribution to conference › Paper, not in proceeding