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- 2008
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2007
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2007) p.221-244(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2005
-
Mark
Multiple Constraints Driven System-on-Chip Test Time Optimization
(
- Contribution to journal › Article
-
Mark
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Introduction to Advanced System-on-Chip Test Design and Optimization
2005) In Frontiers in Electronic Testing(
- Book/Report › Book
- 2004
-
Mark
Integrating Core Selection in the SOC Test Solution Design-Flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2003
-
Mark
Test Resource Partitioning and Optimization for SOC Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2002
-
Mark
Power Constrained Preemptive TAM Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Integrated Test Scheduling, Test Parallelization and TAM Design
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding