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- 2019
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Mark
Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
- Master (Two yrs)
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Mark
Statistical Approach for the Design of Refresh-Free eDRAM with Retention Timing Constraint
- Master (Two yrs)
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Mark
Reconfigurable Instrument Access Network with a Functional Port Interface
- Master (Two yrs)
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Mark
DSP Design With Hardware Accelerator For Convolutional Neural Networks
- Master (Two yrs)
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Mark
Implementation of an 8-bit Dynamic Fixed-Point Convolutional Neural Network for Human Sign Language Recognition on a Xilinx FPGA Board
- Master (Two yrs)
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Mark
Beamforming Solutions for Efficient Link Setup and Link Maintenance in mmWave Communication Systems
- Master (Two yrs)
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Mark
Machine Learning Technique for Uplink Link Adaptation in 5G NR RAN at Millimeter Wave Frequencies
- Master (Two yrs)
- 2018
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Mark
Implementation and Benchmarking of a Crypto Processor for a NB-IoT SoC Platform
- Master (Two yrs)
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Mark
Hardware-software model co-simulation for GPU IP development
- Master (Two yrs)
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Mark
Ethernet Bypass Switch
(2018) In Master Thesis Written Report EITM02 20181
Department of Electrical and Information Technology- Master (Two yrs)