Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
(2018) 63rd IEEE International Electron Devices Meeting, IEDM 2017 Part F134366. p.1-17- Abstract
We demonstrate a process to vary the gate-length of vertical MOSFETs on the same sample with high accuracy and high performance. Fabricated vertical InAs/InGaAs MOSFETs on Si have gate length ranging from 25 nm to 140 nm. The results shown are from single nanowire transistors as well as arrays with nanowires ranging from 80 to 500 nanowires. The devices show good yield and clear scaling trends. We demonstrate a device with gm = 2.4 mS/μm and a device with Ion = 407 μA/μm at Ioff = 100 nA/μm and VDD = 0.5 V, which both are record values for vertical MOSFETs. This is the first demonstration of vertical MOSFETs having gatelengths comparable to the state-of-the-art lateral III-V MOSFETs.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/757899fa-dc61-4099-a2e4-0842881ac3f0
- author
- Kilpi, Olli Pekka LU ; Svensson, Johannes LU and Wernersson, Lars Erik LU
- organization
- publishing date
- 2018-01-23
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2017 IEEE International Electron Devices Meeting, IEDM 2017
- volume
- Part F134366
- pages
- 1 - 17
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 63rd IEEE International Electron Devices Meeting, IEDM 2017
- conference location
- San Francisco, United States
- conference dates
- 2017-12-02 - 2017-12-06
- external identifiers
-
- scopus:85045181315
- ISBN
- 9781538635599
- DOI
- 10.1109/IEDM.2017.8268408
- language
- English
- LU publication?
- yes
- id
- 757899fa-dc61-4099-a2e4-0842881ac3f0
- date added to LUP
- 2018-04-23 10:03:50
- date last changed
- 2022-04-25 06:48:09
@inproceedings{757899fa-dc61-4099-a2e4-0842881ac3f0, abstract = {{<p>We demonstrate a process to vary the gate-length of vertical MOSFETs on the same sample with high accuracy and high performance. Fabricated vertical InAs/InGaAs MOSFETs on Si have gate length ranging from 25 nm to 140 nm. The results shown are from single nanowire transistors as well as arrays with nanowires ranging from 80 to 500 nanowires. The devices show good yield and clear scaling trends. We demonstrate a device with g<sub>m</sub> = 2.4 mS/μm and a device with I<sub>on</sub> = 407 μA/μm at I<sub>off</sub> = 100 nA/μm and V<sub>DD</sub> = 0.5 V, which both are record values for vertical MOSFETs. This is the first demonstration of vertical MOSFETs having gatelengths comparable to the state-of-the-art lateral III-V MOSFETs.</p>}}, author = {{Kilpi, Olli Pekka and Svensson, Johannes and Wernersson, Lars Erik}}, booktitle = {{2017 IEEE International Electron Devices Meeting, IEDM 2017}}, isbn = {{9781538635599}}, language = {{eng}}, month = {{01}}, pages = {{1--17}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si}}, url = {{https://lup.lub.lu.se/search/files/50759347/IEDM17_final.pdf}}, doi = {{10.1109/IEDM.2017.8268408}}, volume = {{Part F134366}}, year = {{2018}}, }