III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si
(2015) In Nano Letters 15(12). p.7898-7904- Abstract
- III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I-on/I-off ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we... (More)
- III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I-on/I-off ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/8551727
- author
- Svensson, Johannes LU ; Dey, Anil LU ; Jacobsson, Daniel LU and Wernersson, Lars-Erik LU
- organization
- publishing date
- 2015
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- III-V, CMOS, nanowire, inverter, NAND, InAs, GaSb, low-power logic, Si
- in
- Nano Letters
- volume
- 15
- issue
- 12
- pages
- 7898 - 7904
- publisher
- The American Chemical Society (ACS)
- external identifiers
-
- wos:000366339600018
- scopus:84949643721
- pmid:26595174
- ISSN
- 1530-6992
- DOI
- 10.1021/acs.nanolett.5b02936
- language
- English
- LU publication?
- yes
- id
- 1cdb040f-9139-4d04-aeb1-53265652aa99 (old id 8551727)
- date added to LUP
- 2016-04-01 14:39:28
- date last changed
- 2023-11-13 10:12:30
@article{1cdb040f-9139-4d04-aeb1-53265652aa99, abstract = {{III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I-on/I-off ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.}}, author = {{Svensson, Johannes and Dey, Anil and Jacobsson, Daniel and Wernersson, Lars-Erik}}, issn = {{1530-6992}}, keywords = {{III-V; CMOS; nanowire; inverter; NAND; InAs; GaSb; low-power logic; Si}}, language = {{eng}}, number = {{12}}, pages = {{7898--7904}}, publisher = {{The American Chemical Society (ACS)}}, series = {{Nano Letters}}, title = {{III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si}}, url = {{https://lup.lub.lu.se/search/files/25064675/III_V_nanowire_CMOS_monolithically_integrated_on_Si_v44_changes_accepted.pdf}}, doi = {{10.1021/acs.nanolett.5b02936}}, volume = {{15}}, year = {{2015}}, }