Test Planning for Core-based Integrated Circuits under Power Constraints
(2017) In Journal of Electronic Testing: Theory and Applications 33(1). p.7-23- Abstract
This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by... (More)
This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time.
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- author
- SenGupta, Breeta LU ; Nikolov, Dimitar LU ; Ingelsson, Urban and Larsson, Erik LU
- organization
- publishing date
- 2017-02-01
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Boundary scan, IEEE 1149.1, JTAG, Power constraint, Stacked integrated circuit, Test cost, Test plan, Test schedule
- in
- Journal of Electronic Testing: Theory and Applications
- volume
- 33
- issue
- 1
- pages
- 17 pages
- publisher
- Springer
- external identifiers
-
- scopus:85010943980
- wos:000394263500003
- ISSN
- 0923-8174
- DOI
- 10.1007/s10836-016-5638-5
- language
- English
- LU publication?
- yes
- id
- 005fe8fb-a182-4322-9768-07e1b9259b5e
- date added to LUP
- 2017-02-14 13:07:16
- date last changed
- 2024-09-15 19:13:23
@article{005fe8fb-a182-4322-9768-07e1b9259b5e, abstract = {{<p>This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time.</p>}}, author = {{SenGupta, Breeta and Nikolov, Dimitar and Ingelsson, Urban and Larsson, Erik}}, issn = {{0923-8174}}, keywords = {{Boundary scan; IEEE 1149.1; JTAG; Power constraint; Stacked integrated circuit; Test cost; Test plan; Test schedule}}, language = {{eng}}, month = {{02}}, number = {{1}}, pages = {{7--23}}, publisher = {{Springer}}, series = {{Journal of Electronic Testing: Theory and Applications}}, title = {{Test Planning for Core-based Integrated Circuits under Power Constraints}}, url = {{http://dx.doi.org/10.1007/s10836-016-5638-5}}, doi = {{10.1007/s10836-016-5638-5}}, volume = {{33}}, year = {{2017}}, }