Ping Lu (Former)

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2013
Mark A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
Lu, Ping ^LU ; Andreani, Pietro ^LU and Liscidini, Antonio (2013) In Analog Integrated Circuits and Signal Processing 76(2). p.195-206
- Contribution to journal › Article
Mark A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
Lu, Ping ^LU ; Andreani, Pietro ^LU and Liscidini, Antonio (2013) IEEE RFIC p.151-154
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
Ye, Dawei ; Lu, Ping ^LU ; Andreani, Pietro ^LU and Zee, Ronan van der (2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 p.169-172
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
Lu, Ping ^LU ; Liscidini, Antonio and Andreani, Pietro ^LU (2013) Norchip conference, 2012
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2012
Mark A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
Lu, Ping ^LU ; Wu, Ying and Andreani, Pietro ^LU (2012) IEEE International Symposium on Circuits and Systems (ISCAS), 2012 p.2593-2596
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
Abdulaziz, Mohammed ^LU ; Shakir, Muhammad ; Lu, Ping ^LU and Andreani, Pietro ^LU (2012) GigaHertz Symposium 2012
- Contribution to conference › Abstract
Mark A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
Lu, Ping ^LU ; Liscidini, Antonio and Andreani, Pietro ^LU (2012) In IEEE Journal of Solid-State Circuits 47(7). p.1626-1635
- Contribution to journal › Article
2011
Mark A 5GHz 90-nm CMOS all digital phase-locked loop
Lu, Ping ^LU and Sjöland, Henrik ^LU (2011) In Analog Integrated Circuits and Signal Processing 66(1). p.49-59
- Contribution to journal › Article
Mark A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
Abdulaziz, Mohammed ^LU ; Shakir, Muhammed ; Lu, Ping ^LU and Andreani, Pietro ^LU (2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark A 0.13µm CMOS ΔΣ PLL FM Transmitter
Wu, Ying ; Liu, Xiaodong ^LU ; Ye, Dawei ; Viswam, Vijay ; Zhu, Lin ; Lu, Ping ^LU ; Radjen, Dejan ^LU and Sjöland, Henrik ^LU (2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding