Erik Larsson
91 – 100 of 175
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2010
-
Mark
On-line Techniques to Adjust and Optimize Checkpointing Frequency
2010) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010) p.29-33(
- Contribution to conference › Paper, not in proceeding
-
Mark
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed and Global Properties at Post-silicon Debug
2010) DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed Global Properties for Post-silicon Debug
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
- 2009
-
Mark
Power-Aware System-Level DfT and Test Planning
2009)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
(
- Contribution to conference › Paper, not in proceeding