Ping Lu (Former)
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- 2015
-
Mark
A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio
2015) 32nd NORCHIP Conference, 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
A 1-1 MASH 2-D Vernier Time-to-Digital Converter with 2nd-order noise shaping
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A TRPC-UWB Transmitter Front-end Based on Wideband IQ Modulator in 0.13-µm CMOS
2014) IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A LC Quadrature VCO With WideTuningRange For TRPC-UWB Application in 0.13-µm CMOS
2014) IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Contribution to journal › Article
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding