Syed Muhammad Yasser Sherazi (Former)
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- 2012
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Mark
A receiver architecture for devices in wireless body area networks
2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems(
- Contribution to journal › Article
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Mark
Sizing of Dual-V-T Gates for Sub-V-T Circuits
2012) IEEE Subthreshold Microelectronics Conference (SubVT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
2012) IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Integration of Full-Custom Cells in a Standard-Cell Based Flow
2012) CDNLive! EMEA, 2012(
- Contribution to conference › Paper, not in proceeding
- 2011
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Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
(
- Contribution to journal › Article
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Mark
Synthesis Strategies for Sub-VT Systems
2011) 20th European Conference on Circuit Theory and Design. ECCTD 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Physical implementation of analog circuits assisted by conventional digital place and route methods
2011) CDNLive! EMEA, 2011(
- Contribution to conference › Other