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SOC Test Time Minimization Under Multiple Constraints

Pouget, Julien; Larsson, Erik LU and Peng, Zebo (2003) 12th IEEE Asian Test Symposium ATS 2003 In [Host publication title missing] p.312-317
Abstract
In this paper, we propose a SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system's power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of interconnections), unit testing with multiple test sets, hierarchical SOCs where cores are embedded in cores, and the sharing of test access mechanism (TAM). Our technique handles these conflicts as well as precedence constraints, which is the order in which the tests has to be applied. We have implemented our algorithm and performed experiments, which... (More)
In this paper, we propose a SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system's power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of interconnections), unit testing with multiple test sets, hierarchical SOCs where cores are embedded in cores, and the sharing of test access mechanism (TAM). Our technique handles these conflicts as well as precedence constraints, which is the order in which the tests has to be applied. We have implemented our algorithm and performed experiments, which shows the efficiency of our approach. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
SOC, system-on-chip, test scheduling, power limitations, test conflicts, test access mechanisms
in
[Host publication title missing]
pages
312 - 317
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
12th IEEE Asian Test Symposium ATS 2003
external identifiers
  • scopus:3142766672
ISSN
1081-7735
ISBN
0-7695-1951-2
DOI
language
English
LU publication?
no
id
ad34f496-d2c6-45c0-8c2d-57961534078a (old id 2341146)
date added to LUP
2012-02-10 13:29:39
date last changed
2018-05-29 11:41:16
@inproceedings{ad34f496-d2c6-45c0-8c2d-57961534078a,
  abstract     = {In this paper, we propose a SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system's power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of interconnections), unit testing with multiple test sets, hierarchical SOCs where cores are embedded in cores, and the sharing of test access mechanism (TAM). Our technique handles these conflicts as well as precedence constraints, which is the order in which the tests has to be applied. We have implemented our algorithm and performed experiments, which shows the efficiency of our approach.},
  author       = {Pouget, Julien and Larsson, Erik and Peng, Zebo},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-1951-2},
  issn         = {1081-7735},
  keyword      = {SOC,system-on-chip,test scheduling,power limitations,test conflicts,test access mechanisms},
  language     = {eng},
  pages        = {312--317},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {SOC Test Time Minimization Under Multiple Constraints},
  url          = {http://dx.doi.org/},
  year         = {2003},
}