Single InAs/GaSb Nanowire Low-Power CMOS Inverter
Dey, Anil LU ; Svensson, Johannes LU ; Borg, Mattias LU
; Ek, Martin
LU
and Wernersson, Lars-Erik
LU
(2012)
In Nano Letters
- Abstract
- III − V semiconductors have so far predom-
inately been employed for n-type transistors in high-frequency
applications. This development is based on the advantageous
transport properties and the large variety of heterostructure
combinations in the family of III − V semiconductors. In
contrast, reports on p-type devices with high hole mobility
suitable for complementary metal − oxide − semiconductor
(CMOS) circuits for low-power operation are scarce. In
addition, the di ffi culty to integrate both n- and p-type devices
on the same substrate without the use of complex bu ff er layers
has hampered the development of III − V based digital logic.
... (More) - III − V semiconductors have so far predom-
inately been employed for n-type transistors in high-frequency
applications. This development is based on the advantageous
transport properties and the large variety of heterostructure
combinations in the family of III − V semiconductors. In
contrast, reports on p-type devices with high hole mobility
suitable for complementary metal − oxide − semiconductor
(CMOS) circuits for low-power operation are scarce. In
addition, the di ffi culty to integrate both n- and p-type devices
on the same substrate without the use of complex bu ff er layers
has hampered the development of III − V based digital logic.
Here, inverters fabricated from single n-InAs/p-GaSb hetero-
structure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high- κ
dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and
o ff -state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold
swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V ds = 0.5 V. Inverter characteristics display a full signal swing
and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although
large parasitic capacitances deform the waveform at higher frequencies. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3127462
- author
- Dey, Anil
LU
; Svensson, Johannes
LU
; Borg, Mattias
LU
; Ek, Martin
LU
and Wernersson, Lars-Erik
LU
- organization
- publishing date
- 2012
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Nanowire, inverter, InAs/GaSb, low-power operation, III-V CMOS
- in
- Nano Letters
- publisher
- The American Chemical Society (ACS)
- external identifiers
-
- pmid:23043243
- wos:000311244400025
- scopus:84869202290
- pmid:23043243
- ISSN
- 1530-6992
- DOI
- 10.1021/nl302658y
- language
- English
- LU publication?
- yes
- additional info
- The information about affiliations in this record was updated in December 2015. The record was previously connected to the following departments: Solid State Physics (011013006), Electrical and information technology (011041010), Polymer and Materials Chemistry (LTH) (011001041)
- id
- 3f6da15d-8c26-47b8-ac5f-b1ccdbb01e02 (old id 3127462)
- date added to LUP
- 2016-04-01 13:04:06
- date last changed
- 2023-11-12 11:35:45
@article{3f6da15d-8c26-47b8-ac5f-b1ccdbb01e02,
abstract = {{III − V semiconductors have so far predom-<br/><br>
inately been employed for n-type transistors in high-frequency<br/><br>
applications. This development is based on the advantageous<br/><br>
transport properties and the large variety of heterostructure<br/><br>
combinations in the family of III − V semiconductors. In<br/><br>
contrast, reports on p-type devices with high hole mobility<br/><br>
suitable for complementary metal − oxide − semiconductor<br/><br>
(CMOS) circuits for low-power operation are scarce. In<br/><br>
addition, the di ffi culty to integrate both n- and p-type devices<br/><br>
on the same substrate without the use of complex bu ff er layers<br/><br>
has hampered the development of III − V based digital logic.<br/><br>
Here, inverters fabricated from single n-InAs/p-GaSb hetero-<br/><br>
structure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high- κ<br/><br>
dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and<br/><br>
o ff -state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold<br/><br>
swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V ds = 0.5 V. Inverter characteristics display a full signal swing<br/><br>
and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although<br/><br>
large parasitic capacitances deform the waveform at higher frequencies.}},
author = {{Dey, Anil and Svensson, Johannes and Borg, Mattias and Ek, Martin and Wernersson, Lars-Erik}},
issn = {{1530-6992}},
keywords = {{Nanowire; inverter; InAs/GaSb; low-power operation; III-V CMOS}},
language = {{eng}},
publisher = {{The American Chemical Society (ACS)}},
series = {{Nano Letters}},
title = {{Single InAs/GaSb Nanowire Low-Power CMOS Inverter}},
url = {{http://dx.doi.org/10.1021/nl302658y}},
doi = {{10.1021/nl302658y}},
year = {{2012}},
}