Millimeter-Wave Vertical III-V Nanowire MOSFET Device-To-Circuit Co-Design
Andric, Stefan LU ; Ohlsson Fhager, Lars LU
and Wernersson, Lars Erik
LU
(2021)
In IEEE Transactions on Nanotechnology
20.
p.434-440
- Abstract
Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies (fT, fmax), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/m. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density... (More)
Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies (fT, fmax), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/m. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/m. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.
(Less)
- author
- Andric, Stefan
LU
; Ohlsson Fhager, Lars
LU
and Wernersson, Lars Erik
LU
- organization
- publishing date
- 2021-05-14
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Capacitance, Circuits, Communication, Feedback, III-V MOSFETs, LNA, Logic gates, Metals, mm-wave, MOSFET, Nanoscale devices, Noise, Performance evaluation, Resistance, RF, Unilateral, Vertical MOSFETs
- in
- IEEE Transactions on Nanotechnology
- volume
- 20
- pages
- 7 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85105883529
- ISSN
- 1536-125X
- DOI
- 10.1109/TNANO.2021.3080621
- language
- English
- LU publication?
- yes
- id
- 4f28c035-5e6b-4e70-b1b4-ab0a293c525b
- date added to LUP
- 2021-06-02 11:53:02
- date last changed
- 2025-04-04 14:08:41
@article{4f28c035-5e6b-4e70-b1b4-ab0a293c525b,
abstract = {{<p>Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies (fT, fmax), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/m. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/m. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.</p>}},
author = {{Andric, Stefan and Ohlsson Fhager, Lars and Wernersson, Lars Erik}},
issn = {{1536-125X}},
keywords = {{Capacitance; Circuits; Communication; Feedback; III-V MOSFETs; LNA; Logic gates; Metals; mm-wave; MOSFET; Nanoscale devices; Noise; Performance evaluation; Resistance; RF; Unilateral; Vertical MOSFETs}},
language = {{eng}},
month = {{05}},
pages = {{434--440}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Transactions on Nanotechnology}},
title = {{Millimeter-Wave Vertical III-V Nanowire MOSFET Device-To-Circuit Co-Design}},
url = {{http://dx.doi.org/10.1109/TNANO.2021.3080621}},
doi = {{10.1109/TNANO.2021.3080621}},
volume = {{20}},
year = {{2021}},
}