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A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs

Netsu, Seiko LU ; Hellenbrand, Markus LU ; Zota, Cezar B. LU ; Miyamoto, Yasuyuki and Lind, Erik LU (2018) In IEEE Journal of the Electron Devices Society 6. p.408-412
Abstract

We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be... (More)

We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.

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author
; ; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Electron traps, FinFETs., high-κ, Hysteresis, hysteresis, III-V, InGaAs, inter face trap, Logic gates, Mathematical model, MOSFET, MOSFETs, Multi-gate, Surface fitting, Surface treatment, trap density
in
IEEE Journal of the Electron Devices Society
volume
6
pages
408 - 412
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85042179791
ISSN
2168-6734
DOI
10.1109/JEDS.2018.2806487
language
English
LU publication?
yes
id
5f2f837d-3a8c-406f-a1e4-8e37b75d5c28
date added to LUP
2018-03-06 09:01:06
date last changed
2024-01-29 12:29:49
@article{5f2f837d-3a8c-406f-a1e4-8e37b75d5c28,
  abstract     = {{<p>We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.</p>}},
  author       = {{Netsu, Seiko and Hellenbrand, Markus and Zota, Cezar B. and Miyamoto, Yasuyuki and Lind, Erik}},
  issn         = {{2168-6734}},
  keywords     = {{Electron traps; FinFETs.; high-&#x03BA;; Hysteresis; hysteresis; III-V; InGaAs; inter face trap; Logic gates; Mathematical model; MOSFET; MOSFETs; Multi-gate; Surface fitting; Surface treatment; trap density}},
  language     = {{eng}},
  month        = {{02}},
  pages        = {{408--412}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Journal of the Electron Devices Society}},
  title        = {{A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs}},
  url          = {{http://dx.doi.org/10.1109/JEDS.2018.2806487}},
  doi          = {{10.1109/JEDS.2018.2806487}},
  volume       = {{6}},
  year         = {{2018}},
}