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InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v

Zota, Cezar B. LU ; Lindelöw, Fredrik LU ; Wernersson, Lars Erik LU and Lind, Erik LU orcid (2016) 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
Abstract

We report on In0.85Ga0.15As nanowire MOSFETs (NWFETs) with record performance in several key VLSI metrics. These devices exhibit ION = 555 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V), ION = 365 μA/μm (at IOFF = 10 nA/μm and VDD = 0.5 V) and a quality factor Q = gm/SS of 40, all of which are the highest reported for a III-V as well as silicon transistor. Furthermore, a highly scalable, self-Aligned gate-last fabrication process is utilized, with a single nanowire as the channel. The devices use a 45° angle between the nanowire and the contacts, which allows for up to a 1.4 times longer gate length at a given pitch.

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author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
article number
7573418
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
conference location
Honolulu, United States
conference dates
2016-06-13 - 2016-06-16
external identifiers
  • scopus:84990943483
ISBN
9781509006373
DOI
10.1109/VLSIT.2016.7573418
language
English
LU publication?
yes
id
650d1a62-e7a9-4150-87bd-7084c71c3ec5
date added to LUP
2016-11-03 07:27:30
date last changed
2025-10-14 11:02:52
@inproceedings{650d1a62-e7a9-4150-87bd-7084c71c3ec5,
  abstract     = {{<p>We report on In<sub>0.85</sub>Ga<sub>0.15</sub>As nanowire MOSFETs (NWFETs) with record performance in several key VLSI metrics. These devices exhibit I<sub>ON</sub> = 555 μA/μm (at I<sub>OFF</sub> = 100 nA/μm and V<sub>DD</sub> = 0.5 V), I<sub>ON</sub> = 365 μA/μm (at I<sub>OFF</sub> = 10 nA/μm and V<sub>DD</sub> = 0.5 V) and a quality factor Q = g<sub>m</sub>/SS of 40, all of which are the highest reported for a III-V as well as silicon transistor. Furthermore, a highly scalable, self-Aligned gate-last fabrication process is utilized, with a single nanowire as the channel. The devices use a 45° angle between the nanowire and the contacts, which allows for up to a 1.4 times longer gate length at a given pitch.</p>}},
  author       = {{Zota, Cezar B. and Lindelöw, Fredrik and Wernersson, Lars Erik and Lind, Erik}},
  booktitle    = {{2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016}},
  isbn         = {{9781509006373}},
  language     = {{eng}},
  month        = {{09}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{InGaAs nanowire MOSFETs with I<sub>ON</sub> = 555 μa/μm at I<sub>OFF</sub> = 100 nA/μm and V<sub>DD</sub> = 0.5 v}},
  url          = {{https://lup.lub.lu.se/search/files/25557527/VLSI_1.000_2_.pdf}},
  doi          = {{10.1109/VLSIT.2016.7573418}},
  year         = {{2016}},
}