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Junctionless tri-gate InGaAs MOSFETs

Zota, Cezar B. LU ; Borg, Mattias LU orcid ; Wernersson, Lars Erik LU and Lind, Erik LU orcid (2017) In Japanese Journal of Applied Physics 56(12).
Abstract

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L g = 25 nm at a nanowire dimension of 7 - 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (N D = 1 - 1019 cm-3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g m = 1.6 mSm and I ON = 160A/m (at I OFF = 100 nA/m and V DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact... (More)

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L g = 25 nm at a nanowire dimension of 7 - 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (N D = 1 - 1019 cm-3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g m = 1.6 mSm and I ON = 160A/m (at I OFF = 100 nA/m and V DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

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author
; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Japanese Journal of Applied Physics
volume
56
issue
12
article number
120306
publisher
Japan Society of Applied Physics
external identifiers
  • scopus:85039153495
ISSN
0021-4922
DOI
10.7567/JJAP.56.120306
project
Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies
language
English
LU publication?
yes
id
97f02b23-50d3-4e72-ae92-026dae8e7646
date added to LUP
2018-01-05 10:56:59
date last changed
2025-03-04 06:06:22
@article{97f02b23-50d3-4e72-ae92-026dae8e7646,
  abstract     = {{<p>We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L <sub>g</sub> = 25 nm at a nanowire dimension of 7 - 16 nm<sup>2</sup>. These devices use a single 7-nm-thick In<sub>0.80</sub>Ga<sub>0.20</sub>As (N <sub>D</sub> = 1 - 10<sup>19</sup> cm<sup>-3</sup>) layer as both channel and contacts. The devices show SS<sub>sat</sub> = 76 mV/dec, peak g <sub>m</sub> = 1.6 mSm and I <sub>ON</sub> = 160A/m (at I <sub>OFF</sub> = 100 nA/m and V <sub>DD</sub> = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.</p>}},
  author       = {{Zota, Cezar B. and Borg, Mattias and Wernersson, Lars Erik and Lind, Erik}},
  issn         = {{0021-4922}},
  language     = {{eng}},
  month        = {{12}},
  number       = {{12}},
  publisher    = {{Japan Society of Applied Physics}},
  series       = {{Japanese Journal of Applied Physics}},
  title        = {{Junctionless tri-gate InGaAs MOSFETs}},
  url          = {{http://dx.doi.org/10.7567/JJAP.56.120306}},
  doi          = {{10.7567/JJAP.56.120306}},
  volume       = {{56}},
  year         = {{2017}},
}