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Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages

Andric, Stefan LU ; Kilpi, Olli-Pekka LU ; Mamidala, Saketh, Ram LU orcid ; Svensson, Johannes LU ; Lind, Erik LU orcid and Wernersson, Lars-Erik LU (2022) In IEEE Transactions on Electron Devices 69(6). p.3055-3055
Abstract
Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an InxGa 1−x As channel with a Ga-composition grading ( x= 1–0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/ μm , in VNW MOSFETs. The field plate consists of a vertically integrated SiO2 layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/ μm , alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field... (More)
Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an InxGa 1−x As channel with a Ga-composition grading ( x= 1–0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/ μm , in VNW MOSFETs. The field plate consists of a vertically integrated SiO2 layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/ μm , alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 Ω⋅μm , and transconductance decrease by 5 μS/μm , per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V. (Less)
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author
; ; ; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Nanowires, MOSFETs, Breakdown, Field plate, InGaAs
in
IEEE Transactions on Electron Devices
volume
69
issue
6
pages
3060 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85129682243
ISSN
0018-9383
DOI
10.1109/TED.2022.3168241
language
English
LU publication?
yes
id
ad5e2071-fb6c-4b53-9691-8c81bff4320c
date added to LUP
2022-05-27 14:16:46
date last changed
2024-07-25 22:01:59
@article{ad5e2071-fb6c-4b53-9691-8c81bff4320c,
  abstract     = {{Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an In<sub>x</sub>Ga <sub>1−x</sub> As channel with a Ga-composition grading ( x= 1–0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/ μm , in VNW MOSFETs. The field plate consists of a vertically integrated SiO<sub>2</sub> layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/ μm , alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 Ω⋅μm , and transconductance decrease by 5 μS/μm , per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V.}},
  author       = {{Andric, Stefan and Kilpi, Olli-Pekka and Mamidala, Saketh, Ram and Svensson, Johannes and Lind, Erik and Wernersson, Lars-Erik}},
  issn         = {{0018-9383}},
  keywords     = {{Nanowires; MOSFETs; Breakdown; Field plate; InGaAs}},
  language     = {{eng}},
  month        = {{04}},
  number       = {{6}},
  pages        = {{3055--3055}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Transactions on Electron Devices}},
  title        = {{Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages}},
  url          = {{http://dx.doi.org/10.1109/TED.2022.3168241}},
  doi          = {{10.1109/TED.2022.3168241}},
  volume       = {{69}},
  year         = {{2022}},
}