gm/Id Analysis of vertical nanowire III–V TFETs
(2023) In Electronics Letters 59(18).- Abstract
- Experimental data on analog performance of gate-all-around III-V vertical Tunnel Field-Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current-mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device... (More)
- Experimental data on analog performance of gate-all-around III-V vertical Tunnel Field-Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current-mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/fa56562e-dee1-4400-b8bc-ae66d116951a
- author
- Rangasamy, Gautham LU ; Zhu, Zhongyunshen LU ; Ohlsson Fhager, Lars LU and Wernersson, Lars-Erik LU
- organization
- publishing date
- 2023-09-18
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Electronics Letters
- volume
- 59
- issue
- 18
- publisher
- IEE
- external identifiers
-
- scopus:85171569994
- ISSN
- 1350-911X
- DOI
- 10.1049/ell2.12954
- language
- English
- LU publication?
- yes
- id
- fa56562e-dee1-4400-b8bc-ae66d116951a
- date added to LUP
- 2023-10-05 22:15:39
- date last changed
- 2023-11-21 23:18:21
@article{fa56562e-dee1-4400-b8bc-ae66d116951a, abstract = {{Experimental data on analog performance of gate-all-around III-V vertical Tunnel Field-Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current-mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage.}}, author = {{Rangasamy, Gautham and Zhu, Zhongyunshen and Ohlsson Fhager, Lars and Wernersson, Lars-Erik}}, issn = {{1350-911X}}, language = {{eng}}, month = {{09}}, number = {{18}}, publisher = {{IEE}}, series = {{Electronics Letters}}, title = {{<i>g</i><sub>m</sub>/<i>I</i><sub>d</sub> Analysis of vertical nanowire III–V TFETs}}, url = {{http://dx.doi.org/10.1049/ell2.12954}}, doi = {{10.1049/ell2.12954}}, volume = {{59}}, year = {{2023}}, }