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- 2014
-
Mark
A Noise Cancelling 0.7-3.8 GHz Resistive Feedback Receiver Front-End in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 4th Order Gm-C Filter with 10MHz Bandwidth and 39dBm IIP3 in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Compensation Technique for Two-Stage Differential OTAs
(
- Contribution to journal › Article
- 2013
-
Mark
A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
(
- Contribution to journal › Article
-
Mark
Area and Power Reduction in DFT Based Channel Estimators for OFDM Systems
2013) NORCHIP Conference, 2013(
- Contribution to conference › Paper, not in proceeding
-
Mark
A 0.7 - 3.7 GHz Six Phase Receiver Front-End With Third Order Harmonic Rejection
2013) IEEE European Solid State Circuits Conference, ESSCIRC 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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