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- 2020
-
Mark
A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs
2020) 2020 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
(
- Contribution to journal › Article
- 2019
-
Mark
A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS
2019) 5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2018
-
Mark
An Accurate Analysis of Phase Noise in CMOS Ring Oscillators
(
- Contribution to journal › Article
- 2017
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Mark
A general theory of phase noise in transconductor-based harmonic oscillators
(
- Contribution to journal › Article
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Mark
On the Remarkable Performance of the Series-Resonance CMOS Oscillator
2017) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
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Mark
A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS
(
- Contribution to journal › Article
- 2016
-
Mark
A continuous-time delta-sigma ADC with integrated digital background calibration
(
- Contribution to journal › Article
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Mark
A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
(
- Contribution to journal › Article