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- 2010
-
Mark
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
(2010) Swedish SoC Conference 2010
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
(2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
- Contribution to conference › Poster
- 2009
-
Mark
Power-Aware System-Level DfT and Test Planning
(2009)
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Deterministic Scan-Chain Diagnosis for Intermittent Faults
(2009) European Test Symposium, ETS 2009
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
- Contribution to conference › Paper, not in proceeding
-
Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
(2009) Frontiers of High Performance Embedded Computing
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
- Contribution to conference › Paper, not in proceeding
