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- 2010
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Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2010) IEEE East-West Design and Test Symposium (EWDTS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Energy-Efficient Redundant Execution for Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Efficient Embedding of Deterministic Test Data
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed and Global Properties at Post-silicon Debug
2010) DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
- 2009
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Mark
Power-Aware System-Level DfT and Test Planning
2009)(
- Chapter in Book/Report/Conference proceeding › Book chapter
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Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
2009) Frontiers of High Performance Embedded Computing(
- Contribution to conference › Paper, not in proceeding
-
Mark
Deterministic Scan-Chain Diagnosis for Intermittent Faults
2009) European Test Symposium, ETS 2009(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding