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- 2013
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Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
- 2012
-
Mark
High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector
(
- Contribution to journal › Article
- 2011
-
Mark
Energy-minimum sub-threshold self-timed circuits using current sensing completion detection
2011) 16th IEEE International Symposium on Asynchronous Circuits and Systems In IET Computers and Digital Techniques 5(4). p.342-353(
- Contribution to journal › Article
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding
2010) 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009 5953. p.347-356(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Minimum-energy sub-threshold self-timed circuits: design methodology and a case study
2010) The 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding