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- 2011
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Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Beyond von Neumann: weakly programmable processor arrays and their programming
2011) First International Software Technology Exchange Workshop(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Multicarrier Faster-than-Nyquist Signaling Transceivers: From Theory to Practice
2011)(
- Thesis › Doctoral thesis (monograph)
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Mark
Formation of the axial heterojunction in GaSb/InAs(Sb) nanowires with high crystal quality
(
- Contribution to journal › Article
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Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
15 nm diameter InAs nanowire MOSFETs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Paper, not in proceeding