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2015
- Contribution to journal Article
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
Ingelsson, Urban; Kumar Goel, Sandeep; Larsson, Erik ^LU and Marinissen, Erik Jan (2015) In IEEE Transactions on Computers 64(12). p.3335-3347 Mark
2014
- Chapter in Book/Report/Conference proceeding Paper in conference proceeding
Test Planning and Test Access Mechanism Design for 3D SICs
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) Swedish System on Chip Conference (SSoCC), 2014 In [Host publication title missing] Mark
- Chapter in Book/Report/Conference proceeding Paper in conference proceeding
Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) IEEE VLSI Test Symposium (VTS) In VLSI Test Symposium (VTS), 2014 IEEE 32nd p.1-6 Mark
2013
- Contribution to conference Paper, not in proceeding
Test Planning for 3D SICs using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2013) Swedish System-On-Chip Conference (SSoCC), 2013 Mark
2012
- Chapter in Book/Report/Conference proceeding Paper in conference proceeding
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) 2012 25th International Conference on VLSI Design In [Host publication title missing] p.442-447 Mark
- Contribution to conference Paper, not in proceeding
Test Planning for Core-based 3D Stacked ICs under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012) Mark
2011
- Chapter in Book/Report/Conference proceeding Paper in conference proceeding
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
Ghani Zadegan, Farrokh ^LU ; Ingelsson, Urban; Asani, Golnaz; Carlsson, Gunnar and Larsson, Erik ^LU (2011) Test Symposium (ATS), 2011 20th Asian In [Host publication title missing] p.525-531 Mark
- Contribution to conference Paper, not in proceeding
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) Swedish System-on-Chip Conference, SSoCC 2011 Mark
- Chapter in Book/Report/Conference proceeding Paper in conference proceeding
Scheduling Tests for 3D Stacked Chips under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011) In [Host publication title missing] p.72-77 Mark
- Contribution to conference Paper, not in proceeding
Test Scheduling for 3D Stacked ICs under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) Mark

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