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- 2015
- Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
- 2014
- Test Planning and Test Access Mechanism Design for 3D SICs
- Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
- 2013
- Test Planning for 3D SICs using ILP
- 2012
- Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
- Test Planning for Core-based 3D Stacked ICs under Power Constraints
- 2011
- Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
- Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
- Test Scheduling for 3D Stacked ICs under Power Constraints
- Scheduling Tests for 3D Stacked Chips under Power Constraints