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- 2013
-
Mark
A 1V SiGe Power Amplifier for 81-86 GHz E-band
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 0.7 - 3.7 GHz Six Phase Receiver Front-End With Third Order Harmonic Rejection
2013) IEEE European Solid State Circuits Conference, ESSCIRC 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A receiver architecture for devices in wireless body area networks
2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems(
- Contribution to journal › Article
-
Mark
A 2.45GHz ultra-low power quadrature front-end in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 70 and 210 GHz LO Generator in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS
2012) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 65-nm CMOS 250uW Quadrature LO Generation Circuit
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
(
- Contribution to journal › Article
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Mark
A CMOS 4.35-mW+22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
(
- Contribution to journal › Article
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Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding