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- 2012
-
Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 65-nm CMOS 250uW Quadrature LO Generation Circuit
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 70 and 210 GHz LO Generator in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.45GHz ultra-low power quadrature front-end in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
Design and analysis of an ultra-low-power LC quadrature VCO
(
- Contribution to journal › Article
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Mark
A 1.6-2.6GHz 29dBm Injection-Locked Power Amplifier with 64% peak PAE in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
(
- Contribution to journal › Article
-
Mark
A CMOS 4.35-mW+22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
(
- Contribution to journal › Article
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article