Erik Larsson
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- 2007
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Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
(2007) p.221-244
- Chapter in Book/Report/Conference proceeding › Book chapter
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Mark
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Improved Scan Chain Diagnosis
(2007) 15th NXP IC Test Symposium
- Contribution to conference › Paper, not in proceeding
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Mark
Protocol Requirements in an SJTAG/IJTAG Environment
(2007) Nordic Test Forum NTF,2007
- Contribution to conference › Paper, not in proceeding
- 2006
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
- Contribution to journal › Article
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Mark
System-on-chip test scheduling with reconfigurable core wrappers
- Contribution to journal › Article
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Mark
Combined Test Data Compression and Abort-on-Fail Test
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO
(2006) 14th Philips Research IC Test Seminar
- Contribution to conference › Paper, not in proceeding
- 2005
-
Mark
Abort-on-Fail Based Test Scheduling
- Contribution to journal › Article
