Erik Larsson
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- 2005
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Mark
Emerging strategies for resource-constrained testing of system chips
2005)(
- Other contribution › Miscellaneous
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Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2005) IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005} p.429-434(
- Contribution to conference › Paper, not in proceeding
-
Mark
Boundary-Scan Test Control in the ATCA Standard
2005)(
- Contribution to conference › Paper, not in proceeding
-
Mark
A Test Data Compression Architecture with Abort-on Fail Capability
2005) IEEE Workshop on RTL and High Level Testing WRTLT(
- Contribution to conference › Paper, not in proceeding
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Mark
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2004
-
Mark
Defect-Aware SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Efficient test solutions for core-based designs
2004) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(5). p.758-775(
- Contribution to journal › Article
-
Mark
Preemptive system-on-chip test scheduling
(
- Contribution to journal › Article
-
Mark
Integrating Core Selection in the SOC Test Solution Design-Flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding