Erik Larsson
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- 2014
-
Mark
Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Planning and Test Access Mechanism Design for 3D SICs
2014) Swedish System on Chip Conference (SSoCC), 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault injection and fault handling: an MPSoC demonstrator using IEEE P1687
2014) 20th IEEE International On-Line Testing Symposium(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Robustness of TAP-based Scan Networks
2014) IEEE International Test Conference, 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Embedded DfT Instrumentation: Design, Access, Retargeting and Case Studies
2013) VLSI Test Symposium (VTS)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning for 3D SICs using ILP
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scenario-Based Network Design for P1687
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Accessing Embedded DfT Instruments with IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
(
- Contribution to journal › Article
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Contribution to journal › Article