Henrik Sjöland
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- 2012
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Mark
A High Efficiency 60GHz Power Amplifier in 65nm CMOS
(
- Contribution to journal › Published meeting abstract
- 2011
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Mark
Design and analysis of an ultra-low-power LC quadrature VCO
(
- Contribution to journal › Article
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Mark
A 1.6-2.6GHz 29dBm Injection-Locked Power Amplifier with 64% peak PAE in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
(
- Contribution to journal › Article
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Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
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Mark
A CMOS 4.35-mW+22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
(
- Contribution to journal › Article
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Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 13dBm 60GHz-band injection locked PA with 36% PAE in 65nm CMOS
2011) APMC 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding