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Test Planning for Core-based 3D Stacked ICs under Power Constraints

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
Abstract
Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.
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author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
Test Architecture, DfT (Design for test), Scan chain, Wrapper Chain, Test Scheduling, Test Time., 3D Stacked Integrated Circuit (SIC)
conference name
IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
language
English
LU publication?
no
id
74c292e9-bfc1-4257-a3d5-e090d512d413 (old id 4305351)
date added to LUP
2014-02-13 11:04:30
date last changed
2016-04-16 12:43:20
@misc{74c292e9-bfc1-4257-a3d5-e090d512d413,
  abstract     = {Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.},
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  keyword      = {Test Architecture,DfT (Design for test),Scan chain,Wrapper Chain,Test Scheduling,Test Time.,3D Stacked Integrated Circuit (SIC)},
  language     = {eng},
  title        = {Test Planning for Core-based 3D Stacked ICs under Power Constraints},
  year         = {2012},
}