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High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm

Kilpi, Olli Pekka LU ; Hellenbrand, Markus LU ; Svensson, Johannes LU ; Persson, Axel R. LU ; Wallenberg, Reine LU ; Lind, Erik LU and Wernersson, Lars Erik LU (2020) In IEEE Electron Device Letters 41(8). p.1161-1164
Abstract

Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 Ωμm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 Ωμm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

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author
; ; ; ; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
InAs, InGaAs, MOSFET, nanowire, TLM, Vertical
in
IEEE Electron Device Letters
volume
41
issue
8
article number
9123921
pages
4 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85089544610
ISSN
0741-3106
DOI
10.1109/LED.2020.3004716
language
English
LU publication?
yes
id
b627cb41-a8e4-403a-9c93-669e132404ed
date added to LUP
2020-08-27 13:41:07
date last changed
2020-12-29 03:50:01
@article{b627cb41-a8e4-403a-9c93-669e132404ed,
  abstract     = {<p>Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 Ωμm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 Ωμm, demonstrating that most of the MOSFET access resistance is located in the contact regions. </p>},
  author       = {Kilpi, Olli Pekka and Hellenbrand, Markus and Svensson, Johannes and Persson, Axel R. and Wallenberg, Reine and Lind, Erik and Wernersson, Lars Erik},
  issn         = {0741-3106},
  language     = {eng},
  number       = {8},
  pages        = {1161--1164},
  publisher    = {IEEE - Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Electron Device Letters},
  title        = {High-Performance Vertical III-V Nanowire MOSFETs on Si with g<sub>m</sub>> 3 mS/μm},
  url          = {http://dx.doi.org/10.1109/LED.2020.3004716},
  doi          = {10.1109/LED.2020.3004716},
  volume       = {41},
  year         = {2020},
}