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Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si

Jönsson, Adam LU ; Svensson, Johannes LU and Wernersson, Lars-Erik LU (2019) 64th IEEE International Electron Devices Meeting p.1-39
Abstract
We use a self-aligned, gate-last process providing n-type (InAs) and p-type (GaSb) MOSFET co-integration with a common gate-stack and demonstrate balanced drive current capability at about 100 μA/μm . By utilizing HSQ-spacers, control of gate-alignment allows to fabricate both n- and p-type devices based on the same type of vertical heterostructure InAs/GaSb nanowire with short gate-lengths down to 60 nm. Refined digital etch techniques, compatible with both sensitive antimonide structures and InAs, enable down to 16 nm diameter GaSb channel regions and 10 nm InAs channels. Balanced performance is showcased for both n- and p-type MOSFETs with Ion=156 μA/μm , at Ioff=100 nA/μm , and 98μA/μm , at |VDS|=0.5 , respectively.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Logic gates, Nanoscale devices, MOSFET, Performance evaluation, Ions, Silicon, Metals
host publication
2018 IEEE International Electron Devices Meeting (IEDM)
pages
1 - 39
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
64th IEEE International Electron Devices Meeting
conference location
San Francisco, United States
conference dates
2018-12-01 - 2018-12-05
external identifiers
  • scopus:85061823566
ISBN
978-1-7281-1987-8
978-1-7281-1988-5
DOI
10.1109/IEDM.2018.8614685
language
English
LU publication?
yes
id
d37499f7-95c9-4156-93e7-fe2cf3dc18b4
date added to LUP
2019-02-19 16:58:20
date last changed
2019-03-27 04:39:05
@inproceedings{d37499f7-95c9-4156-93e7-fe2cf3dc18b4,
  abstract     = {We use a self-aligned, gate-last process providing n-type (InAs) and p-type (GaSb) MOSFET co-integration with a common gate-stack and demonstrate balanced drive current capability at about 100 μA/μm . By utilizing HSQ-spacers, control of gate-alignment allows to fabricate both n- and p-type devices based on the same type of vertical heterostructure InAs/GaSb nanowire with short gate-lengths down to 60 nm. Refined digital etch techniques, compatible with both sensitive antimonide structures and InAs, enable down to 16 nm diameter GaSb channel regions and 10 nm InAs channels. Balanced performance is showcased for both n- and p-type MOSFETs with Ion=156 μA/μm , at Ioff=100 nA/μm , and 98μA/μm , at |VDS|=0.5 , respectively.},
  author       = {Jönsson, Adam and Svensson, Johannes and Wernersson, Lars-Erik},
  isbn         = {978-1-7281-1987-8},
  keyword      = {Logic gates,Nanoscale devices,MOSFET,Performance evaluation,Ions,Silicon,Metals},
  language     = {eng},
  location     = {San Francisco, United States},
  month        = {01},
  pages        = {1--39},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si},
  url          = {http://dx.doi.org/10.1109/IEDM.2018.8614685},
  year         = {2019},
}