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Electrical Characterization of III-V Nanostructure

Shiri Babadi, Aein LU (2016)
Abstract
This thesis investigates the electronic properties of a number of novel III-V materials and material combinations for transistor applications. In particular, high-κ/InAs metal-oxide-semiconductor (MOS) structures and transport properties of GaSb nanowires have been studied. III-V semiconductors are potential candidates to replace Si-based electronics due to their outstanding electron transport properties.
One of the main challenges in the performance of III-V MOS Field-Effect Transistors (MOSFETs) is the integration of high quality high-κ gate oxides. The quality of the oxide and the oxide-semiconductor interface affects the density of trapped charges which subsequently affects the device performance. The first part of the thesis is... (More)
This thesis investigates the electronic properties of a number of novel III-V materials and material combinations for transistor applications. In particular, high-κ/InAs metal-oxide-semiconductor (MOS) structures and transport properties of GaSb nanowires have been studied. III-V semiconductors are potential candidates to replace Si-based electronics due to their outstanding electron transport properties.
One of the main challenges in the performance of III-V MOS Field-Effect Transistors (MOSFETs) is the integration of high quality high-κ gate oxides. The quality of the oxide and the oxide-semiconductor interface affects the density of trapped charges which subsequently affects the device performance. The first part of the thesis is focused on studying the electrical properties of high-κ/InAs material system. A theoretical model of MOS capacitance-voltage (C-V) response is developed for narrow band gap semiconductors to quantify the densities of InAs-oxide interface and border traps. Different deposition conditions and surface passivation techniques are examined to minimize the trap densities. The optimized structure shows trap densities in the order of 1012 cm-2eV-1, which is comparable to the state-of-the-art high-κ on other high-electron-mobility III-Vs, such as InGaAs.
The second part of the thesis discusses the transport properties of GaSb nanowires. The electrical properties of the nanowires are characterized by fabricating lateral nanowire-based Field-Effect transistors. The thesis further explores a strategy for boosting the mobility in GaSb nanowires using strained GaSb/InGaAs core-shell nanowires.
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author
supervisor
opponent
  • Professor McIntyre, Paul, Stanford University, USA
organization
publishing date
type
Thesis
publication status
published
subject
keywords
High-κ, Metal-Oxide-Semicondcutor capacitors, MOSCAPs, III-V semiconductors, InAs, GaSb, interface traps, border traps, C-V, Simulations, Nanowire, MOSFET, Fabrication
publisher
Department of Electrical and Information Technology, Lund University
defense location
Lecture hall E:1406, building E, Ole Römers väg 3, Lund University, Faculty of Engineering LTH, Lund
defense date
2016-11-11 10:15
ISBN
978-91-7623-981-0
978-91-7623-980-3
language
English
LU publication?
yes
id
d4b58ef4-a034-45d2-a362-8be67a60a577
date added to LUP
2016-10-17 09:53:48
date last changed
2016-11-03 11:00:32
@phdthesis{d4b58ef4-a034-45d2-a362-8be67a60a577,
  abstract     = {This thesis investigates the electronic properties of a number of novel III-V materials and material combinations for transistor applications. In particular, high-κ/InAs metal-oxide-semiconductor (MOS) structures and transport properties of GaSb nanowires have been studied. III-V semiconductors are potential candidates to replace Si-based electronics due to their outstanding electron transport properties. <br/>One of the main challenges in the performance of III-V MOS Field-Effect Transistors (MOSFETs) is the integration of high quality high-κ gate oxides. The quality of the oxide and the oxide-semiconductor interface affects the density of trapped charges which subsequently affects the device performance. The first part of the thesis is focused on studying the electrical properties of high-κ/InAs material system. A theoretical model of MOS capacitance-voltage (C-V) response is developed for narrow band gap semiconductors to quantify the densities of InAs-oxide interface and border traps. Different deposition conditions and surface passivation techniques are examined to minimize the trap densities. The optimized structure shows trap densities in the order of 1012 cm-2eV-1, which is comparable to the state-of-the-art high-κ on other high-electron-mobility III-Vs, such as InGaAs. <br/>The second part of the thesis discusses the transport properties of GaSb nanowires. The electrical properties of the nanowires are characterized by fabricating lateral nanowire-based Field-Effect transistors. The thesis further explores a strategy for boosting the mobility in GaSb nanowires using strained GaSb/InGaAs core-shell nanowires.<br/>},
  author       = {Shiri Babadi, Aein},
  isbn         = {978-91-7623-981-0 },
  keyword      = {High-κ,Metal-Oxide-Semicondcutor capacitors,MOSCAPs,III-V semiconductors,InAs,GaSb,interface traps,border traps,C-V,Simulations,Nanowire,MOSFET,Fabrication},
  language     = {eng},
  month        = {10},
  publisher    = {Department of Electrical and Information Technology, Lund University},
  school       = {Lund University},
  title        = {Electrical Characterization of III-V Nanostructure},
  year         = {2016},
}