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- 2004
-
Mark
A Technique for Optimization of System-on-Chip Test Data Transportation
(
- Contribution to conference › Paper, not in proceeding
- 2003
-
Mark
A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Time Minimization Under Multiple Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Defect Probability-based System-On-Chip Test Scheduling
2003) 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS 03,2003 p.25-32(
- Contribution to conference › Paper, not in proceeding
-
Mark
System-on-Chip Test Scheduling based on Defect Probability
2003)(
- Other contribution › Miscellaneous
-
Mark
Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
2003) 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 p.385-392(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2002
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
(
- Contribution to journal › Article
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
2002) p.21-36(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Integrated Test Scheduling, Test Parallelization and TAM Design
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding