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- 2013
-
Mark
Class-D CMOS Oscillators
(
- Contribution to journal › Article
-
Mark
A Push-Pull Class-C CMOS VCO
(
- Contribution to journal › Article
-
Mark
Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation
2013)(
- Thesis › Doctoral thesis (monograph)
-
Mark
A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
(
- Contribution to journal › Article
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
-
Mark
Receiver Front-Ends in CMOS with Ultra-Low Power Consumption
2013)(
- Thesis › Doctoral thesis (compilation)
- 2012
-
Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article
- 2011
-
Mark
Design and analysis of an ultra-low-power LC quadrature VCO
(
- Contribution to journal › Article
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Mark
A 1.6-2.6GHz 29dBm Injection-Locked Power Amplifier with 64% peak PAE in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article