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- 2024
-
Mark
A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS
(
- Contribution to journal › Article
- 2022
-
Mark
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
(
- Contribution to journal › Article
- 2021
-
Mark
Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications
2021)(
- Thesis › Doctoral thesis (compilation)
- 2020
-
Mark
A Decade Frequency Range CMOS Power Amplifier for Sub-6-GHz Cellular Terminals
(
- Contribution to journal › Article
-
Mark
An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping
2020) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
- 2019
-
Mark
A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS
(
- Contribution to journal › Article
-
Mark
Integrated Transmitters for Cellular User Equipment–Wideband CMOS Power Amplifiers and Antenna Impedance Tuners
2019)(
- Thesis › Doctoral thesis (compilation)
- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article
-
Mark
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
(
- Contribution to journal › Article
- 2017
-
Mark
Digital Phase Locked Loops for Radio Frequency Synthesis
2017)(
- Thesis › Doctoral thesis (monograph)
-
Mark
Ultra-wideband transmitter design based on a new transmitted reference pulse cluster
(
- Contribution to journal › Article
- 2016
-
Mark
Ultra-low Voltage Embedded Memories – Design Aspects and a Biomedical Use-case
2016)(
- Thesis › Doctoral thesis (compilation)
-
Mark
A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process
(
- Contribution to journal › Article
- 2015
-
Mark
III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si
(
- Contribution to journal › Article
-
Mark
A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
Continuous-Time Delta-Sigma Modulators for Wireless Communication
2014) In Series of licentiate and doctoral dissertations(
- Thesis › Doctoral thesis (compilation)
-
Mark
A Class-D CMOS DCO with an on-chip LDO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Miniaturized Marchand Balun in CMOS With Improved Balance for Millimeter-Wave Applications
(
- Contribution to journal › Article
-
Mark
Lessons from Ten Years of the International Master’s Program in System-on-Chip
2014) The 10th European Workshop on Microelectronics Education (EWME 2014)(
- Contribution to conference › Paper, not in proceeding
- 2013
-
Mark
Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation
2013)(
- Thesis › Doctoral thesis (monograph)
-
Mark
A Push-Pull Class-C CMOS VCO
(
- Contribution to journal › Article
-
Mark
A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
(
- Contribution to journal › Article
-
Mark
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
(
- Contribution to journal › Article
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
-
Mark
Receiver Front-Ends in CMOS with Ultra-Low Power Consumption
2013)(
- Thesis › Doctoral thesis (compilation)
-
Mark
Class-D CMOS Oscillators
(
- Contribution to journal › Article
- 2012
-
Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article
- 2011
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Micro- and Millimeter Wave CMOS Beamforming Receivers
2011)(
- Thesis › Doctoral thesis (compilation)
-
Mark
Design and analysis of an ultra-low-power LC quadrature VCO
(
- Contribution to journal › Article
-
Mark
A 1.6-2.6GHz 29dBm Injection-Locked Power Amplifier with 64% peak PAE in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
A technique for improving gain and noise figure of common-gate wideband LNAs
(
- Contribution to journal › Article
-
Mark
A 90-nm CMOS +11dBm IIP3 4mW dual-band LNA for cellular handsets
(
- Contribution to journal › Letter
-
Mark
Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier
2010)(
- Thesis › Doctoral thesis (compilation)
-
Mark
A 4.35-mW +22-dBm IIP3 continuously tunable channel select filter for WLAN/WiMax receivers in 90-nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
K-band receiver front-ends in 0.13um CMOS using carrier technology
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 175uW 100MHz-2GHz inductorless receiver frontend in 65nm CMOS
2010) NORCHIP Conference, 2010(
- Contribution to conference › Paper, not in proceeding
- 2009
-
Mark
Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters
(
- Contribution to journal › Article
-
Mark
A compact CMOS MEMS microphone with 66dB SNR
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Microwave CMOS Beamforming Transmitters
2008) In Department of Electrical and Information Technology, Series of licentiate and doctoral theses 12.(
- Thesis › Doctoral thesis (compilation)
-
Mark
A 1W Class-D Audio Power Amplifier in a 0.35um CMOS Process
2008) Norchip Conference, 2008(
- Contribution to conference › Paper, not in proceeding
-
Mark
Two 130nm CMOS class-D RF power amplifiers suitable for polar transmitter architectures
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Microwave CMOS LNAs and VCOs - Using Passives On-Chip, Above Chip, and Off-Chip
2008)(
- Thesis › Doctoral thesis (compilation)
-
Mark
60 GHz 130-nm CMOS Second Harmonic Power Amplifiers
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM
2008) Norchip Conference, 2008(
- Contribution to conference › Paper, not in proceeding
-
Mark
A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2007
-
Mark
Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network
(
- Contribution to journal › Article