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A Self-aligned Gate-last Process applied to All-III-V CMOS on Si

Jonsson, Adam LU ; Svensson, Johannes LU and Wernersson, Lars Erik LU (2018) In IEEE Electron Device Letters 39(7). p.935-938
Abstract
Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are
co-processed and co-integrated using a gate-last process, enabling short
gate-lengths (Lg=40 nm) and allowing selective digital etching of the
channel. Two different common gate-stacks, including various
pre-treatments, were compared and evaluated. The process was optimized
to achieve high n-type performance while demonstrating p-type operation.
The best n-type device is scaled down to 12 nm diameter and has a peak
transconductance of 2.6 mS/μm combined with a low Ron of 317 Ω·μm while
the p-type exhibit 74 μS/μm. In spite of increased complexity due to
co-integration, our n-type InAs transistors demonstrate increased
... (More)
Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are
co-processed and co-integrated using a gate-last process, enabling short
gate-lengths (Lg=40 nm) and allowing selective digital etching of the
channel. Two different common gate-stacks, including various
pre-treatments, were compared and evaluated. The process was optimized
to achieve high n-type performance while demonstrating p-type operation.
The best n-type device is scaled down to 12 nm diameter and has a peak
transconductance of 2.6 mS/μm combined with a low Ron of 317 Ω·μm while
the p-type exhibit 74 μS/μm. In spite of increased complexity due to
co-integration, our n-type InAs transistors demonstrate increased
drive-current, 1.8 mA/μm, compared to earlier publications. (Less)
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
CMOS, GaSb, III-V, InAs, MOSFET, nanowire, Vertical
in
IEEE Electron Device Letters
volume
39
issue
7
pages
935 - 938
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85047019807
ISSN
0741-3106
DOI
10.1109/LED.2018.2837676
language
English
LU publication?
yes
id
357118b8-2439-4b22-b9bb-eb861579c189
date added to LUP
2018-05-29 15:08:18
date last changed
2022-04-17 20:49:02
@article{357118b8-2439-4b22-b9bb-eb861579c189,
  abstract     = {{Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are <br>
co-processed and co-integrated using a gate-last process, enabling short<br>
 gate-lengths (Lg=40 nm) and allowing selective digital etching of the <br>
channel. Two different common gate-stacks, including various <br>
pre-treatments, were compared and evaluated. The process was optimized <br>
to achieve high n-type performance while demonstrating p-type operation.<br>
 The best n-type device is scaled down to 12 nm diameter and has a peak <br>
transconductance of 2.6 mS/μm combined with a low Ron of 317 Ω·μm while <br>
the p-type exhibit 74 μS/μm. In spite of increased complexity due to <br>
co-integration, our n-type InAs transistors demonstrate increased <br>
drive-current, 1.8 mA/μm, compared to earlier publications.}},
  author       = {{Jonsson, Adam and Svensson, Johannes and Wernersson, Lars Erik}},
  issn         = {{0741-3106}},
  keywords     = {{CMOS; GaSb; III-V; InAs; MOSFET; nanowire; Vertical}},
  language     = {{eng}},
  number       = {{7}},
  pages        = {{935--938}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Electron Device Letters}},
  title        = {{A Self-aligned Gate-last Process applied to All-III-V CMOS on Si}},
  url          = {{https://lup.lub.lu.se/search/files/50756363/EDL_2018_CMOS_open_access_Adam.pdf}},
  doi          = {{10.1109/LED.2018.2837676}},
  volume       = {{39}},
  year         = {{2018}},
}