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- 2007
-
Mark
Extended STAPL as SJTAG Engine
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
(
- Contribution to journal › Article
-
Mark
Improved Scan Chain Diagnosis
2007) 15th NXP IC Test Symposium(
- Contribution to conference › Paper, not in proceeding
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
2007) Nordic Test Forum NTF,2007(
- Contribution to conference › Paper, not in proceeding
- 2006
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-chip test scheduling with reconfigurable core wrappers
(
- Contribution to journal › Article
-
Mark
Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
(
- Contribution to journal › Article
-
Mark
Combined Test Data Compression and Abort-on-Fail Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding