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- 2013
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Mark
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
(
- Contribution to journal › Article
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Mark
Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
(
- Contribution to journal › Article
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Mark
A 9MHz Filtering ADC with Additional 2nd-Order Delta-Sigma Modulator Noise Suppression
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Contribution to journal › Article
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
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Mark
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference
(
- Contribution to journal › Debate/Note/Editorial
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Mark
A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
2012) In Analog Integrated Circuits and Signal Processing(
- Contribution to journal › Article
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Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article