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- 2017
-
Mark
A low latency and area efficient FFT processor for massive MIMO systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2005
-
Mark
A scalable pipelined complex valued matrix inversion architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2003
-
Mark
Providing flexibility in a convolutional encoder
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
FPGA implementation of real-time image convolutions with three level of memory hierarchy
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding