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- 2010
-
Mark
Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
(
- Contribution to journal › Article
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Mark
Low power analog channel decoder in sub-threshold 65nm CMOS
2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)(
- Contribution to conference › Paper, not in proceeding
- 2009
-
Mark
A Transmitter Architecture for Faster-than-Nyquist Signaling Systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2008
-
Mark
Optimization and implementation of a Viterbi decoder under flexibility constraints
(
- Contribution to journal › Article
- 2005
-
Mark
Architectural considerations for rate-flexible trellis processing blocks
2005) IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, 2005 p.1076-1080(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Area and power efficient trellis computational blocks in 0.13μm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2004
-
Mark
A simplified computational kernel for trellis-based decoding
(
- Contribution to journal › Article
- 2003
-
Mark
Providing flexibility in a convolutional encoder
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding